SU1339550A1  Device for rounding off sum and difference of binarycoded numbers with floating point  Google Patents
Device for rounding off sum and difference of binarycoded numbers with floating point Download PDFInfo
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 SU1339550A1 SU1339550A1 SU864067821A SU4067821A SU1339550A1 SU 1339550 A1 SU1339550 A1 SU 1339550A1 SU 864067821 A SU864067821 A SU 864067821A SU 4067821 A SU4067821 A SU 4067821A SU 1339550 A1 SU1339550 A1 SU 1339550A1
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Abstract
The invention relates to digital computing and can be used in a digital computer to create highprecision arithmetic devices for adding and subtracting binary floatingpoint numbers presented in a return code. The purpose of the invention is to improve the accuracy of calculations. This goal is achieved due to the correction of both the denormalized term and the normalized result, which have one bit more than the main machine word. The correction of the denormalized term is performed by sending a significant digit to its least significant bit, if at least one significant digit was rejected during the denormalization. The correction of a result normalized and truncated by one least significant bit is achieved by filling a significant digit into the younger one of its main bits, if at least one significant digit was dropped during normalization and truncation. The device contains a register of 1 operand with an additional bit, register 2 results with an additional bit, two triggers 3.4. characters, control inputs for denormalization 5, normalization to the right 6 and completion of normalization 7, element OR 8, additional bits 9, 10 registers 1,2, least significant bit II of register 2, two elements EXCLUSIVE OR 12,13, four elements AND 14 17. 1 Il. 6 (L with 00 with SP ate
Description
The invention relates to digital computing and can be used in a digital computer to create highprecision arithmetic devices for adding and subtracting binary floatingpoint numbers presented in a return code.
The purpose of the invention is to improve the accuracy of calculations.
The drawing shows the functional scheme of the device.
The device contains a register of 1 operand with an additional bit, a register of result 2 with an additional bit, triggers of 3 and 4 digits of the denormalizable number and result, inputs 5–7 of the control of denormalization. Normalization to the right and the end of normalization, the element OR 8, the additional bits 9 and 10 of registers 1 and 2, the lower bit of 11 registers 2, the elements EXCLUSIVE OR 12 and 13 and four elements AND 1417.
The device works as follows.
The rounding of the sum or difference of two floating point numbers represented in the reverse code is that both the denormalized term and the normalized result are corrected. The denormalized number is corrected by sending a significant digit to its additional digit, provided that in the process of denormalization, at least one significant digit was advanced from this bit to the right. Correction of a normalized and truncated by an additional bit of the result is accomplished by means of tki in his younger bit of the significant figures in the case, if the normalizing and truncating bta discarded hot znachascha least one digit. In this case, the significant digit dp of a positive binary number in the reverse code is 1, and for a negative one, O.
Before the device starts operation, trigger 3 and the register are entered, respectively, the sign and reverse binary code of the term mantissa with a smaller order, and in case of equality of the order of terms, the sign and binary code of the mantissa of one of the terms.
If the orders of numbers are different, then a code denormalization occurs, 10
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a move in register 1. ila the shift control input to the right of this register in the course of 5 a signal is given
1, with the result that the code in register 1 is shifted to the right by one bit. At the same time, the offset bit is lost. Before the code is shifted to the right, the signal from the output of the extra bit 9 of register 1 is fed to the input of the EXCLUSIVE OR 12 element, on another input of which a signal from the output of the trigger 3 characters of the denormalizable number acts. As a result, signal 1 is active in the code of the EXCLUSIVE OR 12 element, if the lower digit 9 of register 1 contains a significant digit, and O otherwise. This signal arrives at the first inputs of elements AND 14 and 15, on the third inputs of which signal 1 acts, arriving at input 5. Depending on whether a significant or insignificant digit is in the extra bit 9 of register 1, elements AND 14, 15 turn out to be open. or closed cl. passing signals from the direct and inverse outputs of trigger 3, respectively, to the zero and single inputs of the additional bit 9. Moreover, by the time these signals arrived at the additional bits of the 9, the digit of the code already shifted by one bit to the right was set (to ensure that if necessary, on the lines connecting the outputs of the elements M 14 and 15 with the inputs of additional bit 9, the corresponding delay elements 1e should be supplied). Thus, if an extra digit is in the extra bit of the 9 not yet shifted code, then the bit of the shifted code will not change, since O, O signals act on the inputs of the auxiliary bit 9. In case the register grid 1 goes out meaningful digit, then the outputs of the elements 14 and 15, depending on whether the sign is positive or negative, has a denormalizable number, combinations of the signals O, 1, or 1, O are used, setting in an additional bit. 9 is a significant digit shifted to the right: 1 in the first case and O in the second. Thus, after the first exit for
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the bit grid of register 1 significant digit in the additional bit 9 of this register will have a significant digit at all subsequent shifts until the end of denormalization. This provides a higher correction of the denormalized number.
Further, normalization of the result of addition or subtraction occurs. The sign and the mantissa in the reverse binary code are respectively in trigger 4 and register 2. If the result is to be normalized to the right, the input I is sent to the shift control right input of input 6, resulting in a shift in code 2 in register 2 bit right. At the same time, the bit advanced out of the register is lost. Prior to shifting the code, the signal from the output of the extra bit 10 of register 2 is fed to the input of the EXCLUSIVE OR 13 element, on another input of which a signal from the trigger output of 3 characters is effective. As a result, the output of the EXCLUSIVE OR 13 element is affected by signal 1, if in additional bit 10 register 2 is a significant digit, and O otherwise. This signal arrives at the first inputs of elements AND 16 and 17, on the third inputs of which signal 1 acts, coming from the output of the element OR 8 at one of the inputs of which signal 1 acts, arriving at input 6. Depending on whether a significant or insignificant digit is in the additional bit 10 of register 2, elements AND 16 and 17 are open or closed to pass signals from the direct and inverse), respectively, the outputs of the trigger 4 to the zero and one inputs of the lower bit, respectively. And by the time of arrival of the indicated ignalov the inputs of the least significant bit 11 is set in the trigger code figure is shifted (to allow this if necessary on lines connecting the outputs of AND gates 16 and 17 to the inputs of the least significant bit corresponding to the delay elements 11 to be delivered). Thus, if in the extra bit of the 10 still unshifted code there is an insignificant digit, then the younger of the
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of the digit shifted by one bit to the right, the code does not change, since at the inputs of the lower digit I1 a set of signals O, O acts. If the digit grid of the register 2 is shifted to a significant digit, then at the outputs of the elements And 16 and 17 Depending on whether a positive or negative sign has a result, combinations of O, 1, or 1, O signals are used, which set the rightnormalized result in the younger bit 11 to a significant result: 1 in the first case and O in the second.
At the moment of the normalization termination, regardless of whether normalization took place to the right or not, signal 1 acting on input 7 acts on one of the inputs of the OR element 8. As a result, the signal of the input of the third inputs of the elements 16 and 17 Correction of the youngest of the main bits 1I of the result is produced by tsak was described earlier.
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Thus, after the termination of normalization in register 2, the binary code of the mantissa of the result corrected by the specified method is found.
The correction of the denatured addend and the result of the device leads to the fact that the error of rounding can have different signs regardless of the signs of the addends and the operation performed. Indeed, let, for example, the ordering of the terms be the same, so that the denormalization does not occur, and, therefore, the denormalized term is not corrected. 5 In this case, the rounding error is the result of the error in normalizing the result associated with dropping the significant digit pulled out of the register's grid during normalization to the right, and truncating the result by an extra bit, as well as the error associated with the significant digit getting into the younger one. bit normalized and truncated result. Since the occurrence of the digit O or 1 in the lowerorder bit of the result is uniform, the sending of the significant digit in this digit in half the cases gives an error that is excellent
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from zero, which in absolute value is greater than the normalization error, and has the opposite sign. Thus, in half of the cases, the rounding error is positive, and in half  negative,
The mathematical expectation of the rounding error arising from the operation of the proposed device is strictly early zero.
Claims (1)
 Formula from. bratisA device for rounding the sum and difference of binarycoded floating point numbers, containing an operand register with an extra bit and a result register with an extra bit, two sign triggers, and the shift register inputs of the operand and result register are connected to the denormalization control input and the input control normalization to the right of the device, respectively, characterized by the fact that, in order to improve the accuracy of calculations, it is with the two elements EXCLUSIVE OR, four AND elements and the AND element And, the output of the additional discharge operand registers connected to the first input of the first exclusiveOR gate whose output is connected to the first inputs of the firstEditor E.Papp Order 4222/38Compiled by O. Berezikova Tehred M. KhodanychCirculation 672 VNIIPI USSR State Committeefor inventions and discoveries 113035, Moscow, Zh35, Raushsk nab., 4/5Production and printing company, Uzhgorod, Projecto st., 4and the second element And, the outputs of which are connected to the zero and single inputs of the additional register bit of the operand, the second inputs of the first element EXCLUSIVE OR and the first element And are connected to the direct output of the first sign trigger, the inverse output of which is connected to the second input of the second element And, the input of which is connected to the third input of the first element I and the control input of the denormalization of the device, the input of the normalization control to the right and the input of the end of the normalization which is connected to the first and second inputs of the el OR, the output of which is connected to the first inputs of the third and fourth elements AND, the outputs of which are connected to the zero and single inputs of the lower digit of the result register, the output of the additional discharge of which is connected to the first input of the second element SUPPLIED OR, the output of which is connected to the second inputs of the third and the fourth element And, the third input of the third element And is connected to the second input of the second element EXCLUSIVE OR and the direct output of the second sign trigger, the inverse output of which is connected to the third input m fourth element I.Proofreader N. Korol Subscription
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SU864067821A SU1339550A1 (en)  19860527  19860527  Device for rounding off sum and difference of binarycoded numbers with floating point 
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Cited By (1)
Publication number  Priority date  Publication date  Assignee  Title 

EP0511971A1 (en) *  19901109  19921111  Adaptive Solutions, Inc.  Unbiased bit disposal apparatus and method 

1986
 19860527 SU SU864067821A patent/SU1339550A1/en active
NonPatent Citations (1)
Title 

Папернов А.А. Учебное пособие по курсу Арифметические и логические основы цифровых машин.М., 1961, с.119121. Карцев М.А. Арифметика цифровых машин.М.: Наука, 1969, с. 326ЗЗЬ * 
Cited By (1)
Publication number  Priority date  Publication date  Assignee  Title 

EP0511971A1 (en) *  19901109  19921111  Adaptive Solutions, Inc.  Unbiased bit disposal apparatus and method 
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